1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically to a multivalue memory including memory cells mainly composed of insulated gate field effect transistors and capable of storing information of three or more values. In this specification, the insulated gate field effect transistor will be called a "MOSFET".
2. Description of Related Art
Referring to FIG. 12, there is shown a block diagram of a prior art semiconductor memory storing multivalue information, which is disclosed by for example Japanese Patent Application Pre-examination Publication No. JP-A-62-257699, (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-62-257699 is available from the Japanese Patent Office and the content of the English abstract JP-A-62-257699 is also incorporated by reference in its entirety into this application).
In the prior art semiconductor memory shown in FIG. 12, a function block 10 includes a memory cell array, an address decoder, and a sense amplifier (not shown in FIG. 12) and has a power supply voltage terminal VCC1, an input terminal VCC2 for receiving a reference potential VC and a data output terminal D which is connected to a data input terminal D of each of a first latch circuit 22, a second latch circuit 24 and a third latch circuit 26. Further, the function block 10 has address input terminals A1 to An, which are connected to address lines A1 to An, respectively.
A control circuit 10 controls a voltage of the reference potential VC, and also controls an operation timing of the latch amplifiers 22, 24 and 26 and an outputting timing of a decoder 30 connected to receive respective outputs of the latch circuits 22, 24 and 26.
Clock output terminals for outputting clock signals CK1, CK2 and CK3 of the control circuit 40 are connected to clock input terminals CK of the latch circuits 22, 24 and 26, respectively. A terminal St of the control circuit 40 is a terminal for receiving a signal for controlling whether or not the control circuit 40 should be activated. This circuit St is connected to an output of a NOR circuit 50, receiving a chip enable signal CE and an output enable signal OE (here, the upper bar means that a low level is active). Therefore, when both of the chip enable signal CE and the output enable signal OE are at the low level, the NOR circuit 50 outputs a high level signal to the terminal St of the control circuit 40, so as to activate the control circuit 40.
The memory cell array included in the function block 10 is constituted of a matrix of memory cells each capable of storing information of three or more values. In the following, an example of storing four values in each memory cell will be described. For example, in order to store four values in each memory cell, it can be exemplified
(1) to set a threshold of a memory cell to four different levels; or PA1 (2) to set a gate length (L) or a gate width (W) of a memory cell to four different values, thereby to set four different current values.
Here, the first named example will be described.
In the above referred Japanese patent publication, the threshold of the memory cell is changed by controlling the amount of electrons injected into a floating gate of the memory cell, but it is well known that the threshold of the memory cell can be also changed by controlling the amount of ions injected into a region directly under a gate of the memory cell.
Here, it is assumed that the lowest one of four thresholds thus set is VT0 (0.5 V), a second lowest threshold is VT1 (1.3 V), a third lowest threshold is VT2 (2.0 V), and the highest threshold is VT3 (4.0 V).
The sense amplifier included in the function block 10 operates to discriminate which of the four thresholds VT0 to VT3 corresponds to the threshold set in the memory cell selected by a given address.
FIG. 14 shows a relation between the reference potential and a potential on an internal node in the sense amplifier by using as a standard potential the potential on the internal node in the sense amplifier when the memory cell having the threshold VT0 is selected.
(1) When the memory cell having the threshold VT0 is selected, the potential on the internal node in the sense amplifier becomes the standard potential, and it is detected that this potential is lower than a reference potential V3b, and it is discriminated to be data (KL)=(00). PA0 (2) When the memory cell having the threshold VT1 is selected, the potential on the internal node in the sense amplifier becomes V3, and it is detected that V3 is higher than the reference potential V3b and lower than a reference potential V2b, and it is discriminated to be data (KL)=(10). PA0 (3) When the memory cell having the threshold VT2 is selected, the potential on the internal node in the sense amplifier becomes V2, and it is detected that V2 is higher than the reference potential V2b and lower than a reference potential V1b, and it is discriminated to be data (KL)=(01). PA0 (4) When the memory cell having the threshold VT3 is selected, the potential on the internal node in the sense amplifier becomes V1, and it is detected that V1 is higher than a reference potential V1b, and it is discriminated to be data (KL)=11). PA0 (1) Time t.sub.1 to t.sub.2 PA0 (2) Time t.sub.2 to t.sub.3 PA0 (3) Time t.sub.3 to t.sub.4 PA0 (4) Time t.sub.4 to t.sub.5 PA0 (5) After Time t.sub.5 PA0 (1) time t.sub.4 to t.sub.5 PA0 (2) After Time t.sub.5
Referring to FIG. 15, there is shown a detailed circuit diagram of a part of the function block 10.
Reference Numeral 101 designates the memory cell array composed of the matrix of memory cells M11, . . . , Mn1, . . . , M1m, . . . , Mnm. X1 to Xn are an output of an X address decoder (not shown) for designating an X address of the memory cell array 101, and Y1 to Ym are an output of a Y address decoder (not shown) for designating a Y address of the memory cell array 101. Each memory cell is set to assume any one of the thresholds VT0 to VT3 mentioned above.
Reference Numeral 103 designates a Y selector for selecting digit lines d1 to dm of the memory cell array 101. This selector 103 is constituted of N-channel enhancement MOSFETs (each called "NE-MOSFET") QY1 to QYm. The outputs X1 to Xn of the X address decoder are connected to word lines, respectively, so that one memory cell is located at each of intersections between the word lines and the digit lines in such a manner that each memory cell is connected between a corresponding digit line and the ground, and a gate of the memory cell is connected to a corresponding word line.
Reference Numeral 102 designates the sense amplifier, which includes a biasing circuit composed of a P-channel enhancement MOSFETs (called "PE-MOSFET") QS111, an NE-MOSFET QS112, and a feedback inverter IS111. The biasing circuit detects a cell current which changes dependently upon the threshold of the selected memory cell.
VSA3 designates the internal node as mentioned above in the sense amplifier. The potential on the internal node VSA3 is determined by a ratio of the current flowing through the selected memory cell to a current driving capability of the PE-MOSFET QS111.
Accordingly, if the threshold of the selected memory cell is VT0, a large cell current flows so that the potential on the internal node VSA3 drops and then balances with the standard potential shown in FIG. 14.
On the other hand, if the threshold of the selected memory cell is VT3, even if the power supply voltage (3 V) is applied to the gate of the selected memory cell, a cell current does not flow, so that the potential on the internal node VSA3 balances with V1 shown in FIG. 14.
When the threshold on the selected memory cell is VT1 or VT2, the potential on the internal node VSA3 is determined by the value of the cell current and balances with V3 or V2 shown in FIG. 14.
The sense amplifier 102 also includes a differential circuit composed of PE-MOSFETs QS121 and QS122 and NE-MOSFETs QS123, QS124 and QS125, and so configured to compare the potential on the internal node VSA3 with the reference potential VC and to amplify a difference therebetween.
For example, if the potential on the internal node VSA3 is higher than the reference potential VC, a potential on a node fA becomes a low level, with the result that an output D of an inverter IS112 becomes a high level.
On the other hand, if the potential on the internal node VSA3 is lower than the reference potential VC, the potential on the node fA becomes the high level, with the result that an output D of an inverter IS112 becomes the low level.
Referring to FIG. 16, there is a timing chart illustrating an operation of the control circuit 40 and potential changes on the internal node VSA3 and the outputs A, B and C of the latch circuits 22, 24 and 26 when the threshold of the selected memory cell is VT1.
Now, an operation of the prior art semiconductor memory storing the multivalue information will be described with reference to FIGS. 12 to 16.
If the high level signal is inputted to the terminal St of the control circuit 40 from the NOR circuit 50, the control circuit 40 starts to operate. The control circuit 40 elevates the reference potential VC stepwise to three different levels in the order of V3b, V2b and V1b, and outputs the clocks CK3, CK2 and CK1 in the order of CK3, CK2 and CK1 and in time with corresponding reference potentials V3b, V2b and V1b. After this sequential operation, the control circuit 40 outputs an output request signal OE to a gate input G of the decoder 30.
Each of the clocks CK3, CK2 and CK1 is set to have a pulse width T giving a sufficient time for data read out in each reference potential to be outputted to the data output terminal D of the function block 10.
Next, explanation will be made on an operation of the sense amplifier, the latch circuits and the decoder when the threshold of the selected memory cell is VT1.
In this period of time, an address is set, and the selected memory cell is determined. In accordance with the threshold (VT1 in this example) of the selected memory cell, a cell current flows, and this cell current is sensed by the sense amplifier so that the potential on the internal node VSA3 balances with V3.
In this period of time, the clock CK3 is brought to the high level so that the latch circuit 26 is activated. The value of the reference potential VC balances with the first reference potential V3b.
At this time, since it becomes VSA3&lt;V3b, the potential of the output D of the sense amplifier becomes the high level. In this condition, since the latch circuit 26 is activated, the potential of the output D of the sense amplifier is transferred to the output of the latch circuit 26, with the result that the input C of the decoder 30 is brought to the high level as shown in FIG. 16. Here, for simplification of the description, it is assumed that the inputs A, B and C of the decoder circuit are set to the high level in an initial stage.
In this period of time, the clock CK2 is brought to the high level so that the latch circuit 24 is activated. The value of the reference potential VC elevates from the V3b and then balances with the second reference potential V2b.
At this time, since it becomes VSA3&lt;V2b, the potential of the output D of the sense amplifier becomes the low level. In this condition, since the latch circuit 24 is activated, the potential of the output D of the sense amplifier is transferred to the output of the latch circuit 24, with the result that the input B of the decoder 30 is brought to the low level from the high level as shown in FIG. 16.
In this period of time, the clock CK1 is brought to the high level so that the latch circuit 22 is activated. The value of the reference potential VC elevates from the V2b and then balances with the third reference potential V1b.
At this time, since it becomes VSA3&lt;V1b, the potential of the output D of the sense amplifier becomes the low level. In this condition, since the latch circuit 22 is activated, the potential of the output D of the sense amplifier is transferred to the output of the latch circuit 22, with the result that the input A of the decoder 30 is brought to the low level from the high level as shown in FIG. 16.
The output request signal OE is brought from the low level to the high level, so that the decoder 30 is put in an output enable condition. In this condition, since the data inputs A, B and C of the decoder are set to {001} until the time t.sub.5, it is discriminated that the selected memory cell is set to have the threshold VT1 as shown in a logic value table of FIG. 13.
In the circuit shown in FIG. 12, since the decoder 30 has the output O of one bit, the data is outputted in a time-division manner. For the data of (KL)=(01) corresponding to the memory cell having the threshold VT1, first, a signal E applied to an input E of the decoder 30 is brought to "0", so that the data of "0" is outputted to the output O of the decoder 30, and then, the signal E is brought to "1", the data of "1" is outputted to the output O of the decoder 30. However, the decoder 30 can have a construction of outputting an output of two bits. In this case, it is possible to output the data of (KL)=(01) as O1 and O2.
Referring to FIG. 17, there is a timing chart illustrating an operation of the control circuit 40 and potential changes on the internal node VSA3 and the outputs A, B and C of the latch circuits 22, 24 and 26 when the threshold of the selected memory cell is VT1, similar to FIG. 16, but when the voltage VCC of the power supply CC varies because of noises in the period of time t.sub.4 to t.sub.5.
In general, in semiconductor memories, when each of various circuits switches, noises occur on the power supply voltage so that a potential of the power supply voltage varies.
Now, an operation in this situation will be described with FIGS. 15 and 17 to 19. Since various waveforms in an operation until time t.sub.4 are the same as those shown in FIG. 16, explanation will be omitted.
In the period of time t.sub.4 to t.sub.5, noises occur on the power supply voltage as shown in FIG. 17, so that the potential of the power supply voltage varies.
First, if the power supply voltage VCC elevates as in a period of time t.sub.41, a power supply voltage of the feedback inverter IS111 in the sense amplifier 102 in FIG. 15 elevates. At this time, a number of Y selectors 103 is connected to a node SC, and therefore, a capacitance associated to the node SC is large (for example, 5 pF). Accordingly, the potential on the node SC is stable. As a result, the feedback inverter IS111 amplifies the potential variation of the power supply voltage VCC, so that the potential on a node SB, which is the output of the feedback inverter IS111, greatly elevates, with the result that QS112 is turned on, and therefore, the potential of the node SA3 greatly drops as shown in the waveform VSA3 in FIG. 17.
To the contrary, if the power supply voltage VCC drops as in a period of time t.sub.42, the power supply voltage of the feedback inverter IS111 in the sense amplifier 102 in FIG. 15 drops. At this time, because of the reason mentioned above, the feedback inverter IS111 amplifies the potential variation of the power supply voltage VCC, so that the potential on the node SB greatly drops, with the result that QS112 is turned off, and therefore, the potential of the node SA3 greatly elevates as shown in the waveform VSA3 in FIG. 17. Thereafter, if the variation in the power supply voltage subsides, the potential of the node SA3 returns to the balanced level.
Here, if the potential of the node SA3 drops, the node SA3 is charged through QS111. However, since the current driving capacity of QS111 is determined taking the value of the cell current into consideration, the current driving capacity of QS111 is ordinarily small, and therefore, the charging speed of the node SA3 is low.
Referring to FIG. 18, there is shown a circuit diagram of one example of the reference potential generating circuit. Reference Numeral 81 designates a circuit for generating the first reference potential V3b. This circuit 81 is composed of NE-MOSFETs QR11 and QR12 series-connected between the power supply voltage VCC and the ground, a connection node between the NE-MOSFETs QR11 and QR12 being connected the terminal VC through a transfer gate composed of a PE-MOSFET QR13 and an NE-MOSFET QR14 connected in parallel to each other and controlled by a pair of complementary pulses .phi..sub.1 and .phi..sub.1B. Therefore, the first reference potential V3b is determined by a threshold of the NE-MOSFET QR12, as shown in the following equation (1). EQU V3b=VTN (1)
Here, for simplification of description, it is considered that the threshold of all NE-MOSFETs is the same and expressed by VTN.
In addition, in order that the value of V3b does not have a dependency upon the power supply voltage as shown in FIG. 19, it is designed that the current driving capacity of QR12 in sufficiently larger than that of QR11.
Reference Numeral 82 designates a circuit for generating the second reference potential V2b. This circuit 82 is composed of NE-MOSFETs QR21, QR22 and QR23 series-connected between the power supply voltage VCC and the ground, a connection node between the NE-MOSFETs QR21 and QR22 being connected the terminal VC through a transfer gate composed of a PE-MOSFET QR24 and an NE-MOSFET QR25 connected in parallel to each other and controlled by a pair of complementary pulses .phi..sub.2 and .phi..sub.2B. Therefore, the second reference potential V2b is determined by a threshold of the NE-MOSFETs QR22 and QR23, as shown in the following equation (2). EQU V2b=2.multidot.VTN (2)
Here, in order that the value of V2b does not have a dependency upon the power supply voltage as shown in FIG. 19, it is designed that the current driving capacity of QR22 and QR23 is sufficiently large than that of QR21.
Reference Numeral 83 designates a circuit for generating the first reference potential V1b. This circuit 83 is composed of NE-MOSFETs QR31, QR32, QR33 and QR34 series-connected between the power supply voltage VCC and the ground, a connection node between the NE-MOSFETs QR31 and QR32 being connected the terminal VC through a transfer gate composed of a PE-MOSFET QR35 and an NE-MOSFET QR36 connected in parallel to each other and controlled by a pair of complementary pulses .phi..sub.3 and .phi..sub.3B. Therefore, the third reference potential V1b is determined by a threshold of the NE-MOSFETs QR32, QR33 and QR34, as shown in the following equation (3). EQU V2b=3.multidot.VTN (3)
Here, in order that the value of V1b does not have a dependency upon the power supply voltage as shown in FIG. 19, it is designed that the current driving capacity of QR32, Q33 and QR34 is sufficiently larger than that of QR31.
Since the reference potential generating circuit is designed as mentioned above, even if the power supply voltage varies as shown in FIG. 17, the reference potential almost never varies.
In the period of time t.sub.4 to t.sub.5, accordingly, VSA3 should be smaller than VC, but if the power supply voltage noise occurs, VSA3 becomes larger than VC, with the result that the output A of the latch circuit 22 changes from the low level to the high level. Namely, an erroneous operation occurs.
Thus, the input data (ABC) of the decoder 30 is set to (101) until time t.sub.5. As seen from the logic value table of FIG. 13, this condition is not allocated in the logic table, and therefore, it is not possible to correctly discriminate that the selected memory cell is set to have the threshold VT1.
The above mentioned example is that the selected memory cell has the threshold VT1 and the power supply voltage noise occurs in the period of time t.sub.4 to t.sub.5. However, when the selected memory cell has the threshold VT0, if the power supply voltage noise occurs in the period of time t.sub.3 to t.sub.4 or in the period of time t.sub.4 to t.sub.5, the potential of the node SA3 varies as the waveform of VSA3 in FIG. 17, and an erroneous operation occurs. Therefore, a data reading cannot be normally performed when the selected memory cell having the threshold VT0 is selected.
In order to overcome this disadvantage, it is considered to elongate the high level period T of each clock. However, this results in delay of the timing where the output request signal OE changes from the low level to the high level. Therefore, the reading speed becomes slow.
As mentioned above, a first problem of the prior art is too sensitive to the power supply voltage noise, because, if the power supply voltage noise occurs, the internal node potential VSA3 of the sense amplifier greatly varies to become higher than the reference potential VC, with the result that the erroneous reading occurs.
A second problem of the prior art is that the reading speed becomes slow if an attempt is made to eliminate the first problem of the prior art. Because, it is necessary to elongate the high level period T of each clock.